1. Technical Field
This invention relates to wafers having integrated circuits and, more particularly, to an electrical testing device for testing the integrated circuits located on a wafer before dicing.
2. Discussion
Current silicon wafers generally contain hundreds of integrated circuits fabricated on a single slice of silicon crystal known as a wafer. Each integrated circuit, chip, or die generally contains from tens to hundreds of thousands and possibly millions of electrical components such as inverters and gates which are interconnected to form electrical circuits. Due to increased density and wafer sizes from advanced technology, wafers are continually being developed which provide for more integrated circuits.
Generally, the individual integrated circuits on a wafer are electrically tested to determine whether the circuits or dies function properly and are therefore good. Electrical testing techniques have been provided for testing integrated circuits that have already been diced and therefore separated from the wafer. However, on-wafer electrical testing for integrated circuits before dicing can greatly improve productivity and yield. This is because handling can be reduced due to greatly reduced part count and defective parts can be identified earlier.
Known testing procedures for testing wafers prior to dicing include employing an array of test probes for mechanically stepped on-wafer electrical testing, such as that provided by an automatic probing station. This technique essentially tests one die or integrated circuit at a time and then moves to another die on the wafer and so on. However, this mechanical stepping technique involves undesirable mechanical movement.
To eliminate the undesirable mechanical movement, a device could be provided which has a sufficient amount of testing probes to test the entire wafer. However, due to the large number of necessary test fixture connections, it is practically impossible to deploy such a one-to-one testing scheme. The large number of connections required would result in a highly complex testing system.
In addition, current testing schemes generally do not provide for testing circuits having contact points close enough to fully meet the requirements of current and future high density wafers. Current testing methods include a technique employing a "bed of nails" approach. The bed of nails approach generally includes a plurality of wires for contacting the wafer. However, the wires have a limited operation distance, are generally easily susceptible to damage and often difficult to align with targeted contact points.
Furthermore, conventional testing approaches generally require some kind of technique for aligning the test circuit with the integrated circuitry to be tested on the wafer. Traditionally, this has been accomplished by visually aligning the wafer with the housing surrounding the test circuit to achieve a predetermined match. However, some of the contacts on the circuit may not properly contact the integrated circuit on the wafer due to misalignment or sometimes due to contraction or expansion of the test circuit. Using conventional approaches, it is necessary that the test circuit contacts match the exact arrangement of the integrated circuitry to within an acceptable tolerance.
It is therefore desirable to provide an on-wafer electrical testing device which has a flexible test circuit that may be accurately aligned with the contact points to be tested on a wafer. It is also desirable to provide a compliant testing circuit that may be easily aligned and also adjusted to accomodate mismatches between the contacts and contact points. It is further desirable to provide a uniform contact between the testing device and the wafer while ensuring dimensional stability thereof.